preliminary data this is preliminary information on a new product now in deve lopment or undergoing evaluation. details are subject to change without notice. august 2008 rev 1 1/10 10 STL15N3LLH5 n-channel 30 v, 0.0045 ? , 15 a, powerflat? (3.3 x 3.3) stripfet? v power mosfet features r ds(on) * q g industry benchmark extremely low on-resistance r ds(on) very low switching gate charge high avalanche ruggedness low gate drive power losses applications switching applications description this product utilizes the 5 th generation of design rules of st?s proprietary stripfet? technology. the lowest available r ds(on) *q g , in this chip scale package, makes this device suitable for the most demanding dc-dc converter applications, where high power density is to be achieved. figure 1. internal schematic diagram type v dss r ds(on) i d STL15N3LLH5 30v <0.0054 ? 15a (1) 1. the value is rated according rthj-pcb powerflat?(3.3x3.3) (chip scale package) table 1. device summary order code marking package packaging STL15N3LLH5 15n3llh5 powerflat? (3.3 x 3.3) tape and reel www.st.com
contents STL15N3LLH5 2/10 contents 1 electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3 test circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 4 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 5 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
STL15N3LLH5 electrical ratings 3/10 1 electrical ratings table 2. absolute maximum ratings symbol parameter value unit v ds drain-source voltage (v gs = 0) 30 v v gs gate-source voltage 22 v i d (1) 1. the value is rated according rthj-pcb drain current (continuous) at t c = 25 c 15 a i d (1) drain current (continuous) at t c =100 c 9.3 a i dm (2) 2. pulse width limited by safe operating area. drain current (pulsed) 60 a p tot (3) 3. the vaule is rated according rthj-c total dissipation at t c = 25 c 50 w p tot (1) total dissipation at t c = 25 c 2 w derating factor 0.4 w/c t j t stg operating junction temperature storage temperature -55 to 150 c table 3. thermal resistance symbol parameter value unit r thj-case thermal resistance junction-case (drain) 2.5 c/w r thj-pcb (1) 1. when mounted on fr-4 board of 1inch2, 2oz cu, t < 10sec thermal resistance junction-pcb 42.8 c/w r thj-pcb (2) 2. steady state thermal resistance junction-pcb 63.5 c/w
electrical characteristics STL15N3LLH5 4/10 2 electrical characteristics (t case =25c unless otherwise specified) table 4. on/off states symbol parameter test conditions min. typ. max. unit v (br)dss drain-source breakdown voltage i d = 250 a, v gs = 0 30 v i dss zero gate voltage drain current (v gs = 0) v ds = max rating, v ds = max rating @125 c 1 10 a a i gss gate body leakage current (v ds = 0) v gs = 22 v 100 na v gs(th) gate threshold voltage v ds = v gs , i d = 250 a 12.5v r ds(on) static drain-source on resistance v gs = 10 v, i d = 7.5 a v gs = 4.5 v, i d = 7.5 a 0.0045 0.006 0.0054 0.0075 ? ? table 5. dynamic symbol parameter test conditions min. typ. max. unit c iss c oss c rss input capacitance output capacitance reverse transfer capacitance v ds =25 v, f=1 mhz, v gs =0 1500 295 39 pf pf pf q g q gs q gd total gate charge gate-source charge gate-drain charge v dd =15 v, i d = 15 a v gs =4.5 v (see figure 3) 12 4 4.7 nc nc nc r g gate input resistance f=1 mhz gate dc bias = 0 test signal level = 20 mv open drain 0.5 1.5 2.5 ?
STL15N3LLH5 electrical characteristics 5/10 table 6. switching times symbol parameter test cond itions min. typ. max. unit t d(on) t r t d(off) t f turn-on delay time rise time turn-off delay time fall time v dd =15 v, i d = 7.5 a, r g =4.7 ?, v gs =4.5 v (see figure 2) 9.3 14.5 22.7 4.5 ns ns ns ns table 7. source drain diode symbol parameter test conditions min. typ. max. unit i sd source-drain current 15 a i sdm (1) 1. pulse width limited by safe operating area source-drain current (pulsed) 60 a v sd (2) 2. pulsed: pulse duration=300s, duty cycle 1.5% forward on voltage i sd =15 a, v gs =0 1.1 v t rr q rr i rrm reverse recovery time reverse recovery charge reverse recovery current i sd =15 a, di/dt = 100 a/s, v dd =20 v, tj=150 c (see figure 7) 25 17.5 1.4 ns nc a
test circuit STL15N3LLH5 6/10 3 test circuit figure 2. switching times test circuit for resistive load figure 3. gate charge test circuit figure 4. test circuit for inductive load switching and diode recovery times figure 5. unclamped inductive load test circuit figure 6. unclamped inductive wavefo rm figure 7. switching time waveform
STL15N3LLH5 package mechanical data 7/10 4 package mechanical data in order to meet environmental requirements, st offers these devices in ecopack? packages. these packages have a lead-free second level interconnect . the category of second level interconnect is marked on the package and on the inner box label, in compliance with jedec standard jesd97. the maximum ratings related to soldering conditions are also marked on the inner box label. ecopack is an st trademark. ecopack specifications are available at: www.st.com
package mechanical data STL15N3LLH5 8/10 powerflat? ( 3 . 3 x 3 . 3 ) mechanical data dim mm inch min typ max min typ max a0. 9 50 1.000 0.0 3 7 0.0 39 a 3 0.200 0.00 8 b 0.2 9 0. 3 40. 39 0.011 0.01 3 0.015 d 3 .200 3 . 3 00 3 .400 0.126 0.12 3 0.1 3 4 d2 2.24 2.2 9 2. 3 4 0.0 88 0.0 9 0 0.0 9 2 e2.20 3 . 3 0 3 .40 0.0 8 6 0.12 3 0.1 338 e2 1.660 1.710 1.760 0.065 0.067 0.06 9 e 0.650 0.025 l 0.40 0.0157 l1 0.45 0.50 0.55 0.017 0.01 9 6 0.021
STL15N3LLH5 revision history 9/10 5 revision history table 8. document revision history date revision changes 25-aug-2008 1 first release
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